Timing extractor, timing extraction method, and demodulator having the timing extractor

ABSTRACT

In a timing component extractor for a digital modulated signal, a frequency converting section  30  receives a complex baseband signal having a symbol rate fs and formed from an I signal and a Q signal, and converts frequency components ±fs/2, which are present in the complex baseband signal as the data changes, to frequency components ±fs/4. The I signal and Q signal of the complex baseband signal are then nonlinearly processed. In other words, multipliers  31, 32  square the I signal and the Q signal, respectively, and an adder  33  adds the respective results of the multipliers  31, 32 . A BPF  34  extracts the frequency components ±fs/2 from the output of the adder  33 , and outputs the extracted frequency components ±fs/2 as a timing signal. Accordingly, processing can be conducted at a sampling frequency which is twice the symbol rate fs. Moreover, timing extraction can be stably conducted without being affected by a carrier frequency offset.

TECHNICAL FIELD

The present invention relates to a timing extractor and a timingextraction method for extracting timing required to demodulate a digitalmodulation system such as a PSK (Phase Shift Keying) system and a QAM(Quadrature Amplitude Modulation) system used in digital satellite TVbroadcasting, digital cable TV broadcasting and the like.

BACKGROUND ART

Japanese Patent No. 2,555,140 (Document 1) describes a method forextracting a timing component in order to demodulate a digital modulatedsignal of a PSK system, a QAM system or the like and reproduceinformation contained in the signal. In this method, a frequencycomponent fs is extracted by nonlinearly processing a frequencycomponent fs/2 (i.e., a frequency component which is ½ times a symbolrate fs) which is present in a digital modulated signal as symbol datachanges.

Since this extraction method uses nonlinear processing, timingextraction can be stably conducted without being affected by a carrierfrequency offset produced by a frequency error of a local oscillatorused in a receiver. In order to extract a frequency component fs,digital signal processing must be conducted at a sampling frequencyhigher than 2fs according to the sampling theorem. A sampling frequencyof 4fs or more is usually used in order to prevent interference.

Japanese Patent Laid-Open Publication No. 5-207082 (Document 2)describes another method for extracting a timing component. In thismethod is extracted a frequency component fs/2 which is present in adigital modulated signal as symbol data changes. The extracted frequencycomponent is then subjected to vector processing, frequency shifting,and double angling. Accordingly, timing extraction can be conducted at asampling frequency 2fs.

Japanese Patent Laid-Open Publication No. 7-226781 (Document 3)describes still another method for extracting a timing component. Inthis method, a frequency component fs is extracted at a samplingfrequency 2fs by nonlinearly processing an averaged digital signal andobtaining the difference between the nonlinearly processed signal and aone-sample delayed version of that signal.

Problems

The method of Document 1 requires digital signal processing at asampling frequency 4fs for stable timing extraction. This results indifficulty in hardware implementation and increased power consumption ifthe symbol rate is high. Even at a low symbol rate, this results inincreased amount of processing per unit time if a DSP is used.

The method of Document 2 is affected by a carrier frequency offsetproduced by a frequency error of a local oscillator used in a receiver,because the method uses vector processing. Such a carrier frequencyoffset prevents accurate timing extraction.

The extraction method of Document 3 uses a sampling frequency 2fs. Anextracted signal therefore causes interference according to the samplingtheorem, thereby preventing stable timing extraction.

DISCLOSURE OF THE INVENTION

The present invention is made in order to solve the above problems, andit is an object of the present invention to provide a timing extractionmethod which enables digital signal processing at a sampling frequencyas low as 2fs as well as facilitates hardware implementation even at ahigh symbol rate fs, and also enables interference-free, stable timingextraction without being affected by a carrier frequency offset.

In order to achieve the above object, according to the presentinvention, the following processing is conducted to demodulate a digitalmodulated signal and reproduce information included in the digitalmodulated signal: a complex baseband signal formed from an I signal anda Q signal is obtained from a digital modulated signal having a symbolrate fs. Positive and negative frequency components of fs/2 included inthe complex baseband signal are converted to such a frequency positionthat does not cause interference with other frequency components. Theresultant I and Q signals are then at least squared. A frequencycomponent which is twice the frequency position is then extracted.

More specifically, a timing extractor according to the present inventionextracts a timing component for determining a symbol from a digitalmodulated signal having a symbol rate fs. The timing extractor includesa frequency converting means for converting positive and negativefrequency components of fs/2 included in a complex baseband signal to afrequency position fm (0<|fm|<fs/2). The complex baseband signal isobtained from the digital modulated signal and formed from an I signaland a Q signal. The timing extractor further includes a nonlinearprocessing means for at least squaring the I signal and the Q signalresulting from frequency conversion by the frequency converting means,and a frequency extracting means for extracting from an output signal ofthe nonlinear processing means a frequency component 2fm, i.e., afrequency component which is twice the frequency position fm, andoutputting the extracted frequency component as a timing signal.

In the above timing extractor, the frequency position fm may be|fm|=fs/2M (where M is an integer of at least two).

In the above timing extractor, M may be M=2 and the frequency positionfm may be |fm|=fs/4.

In the above timing extractor, M may be M=4 and the frequency positionfm may be |fm|=fs/8.

In the above timing extractor, the frequency converting means mayinclude a filtering means for removing in advance from the complexbaseband signal a frequency component which will become an aliasingdistortion component for the frequency component 2fm included in theoutput signal of the nonlinear processing means.

In the above timing extractor, the frequency converting means mayinclude a first frequency shifting means for shifting a frequency of thecomplex baseband signal in a frequency increasing direction, and asecond frequency shifting means for shifting a frequency of the complexbaseband signal in a frequency decreasing direction.

In the above timing extractor, the frequency converting means mayinclude a frequency shifting means for shifting a frequency of thecomplex baseband signal in a frequency increasing direction and afrequency decreasing direction by fs/2.

In the above timing extractor, the frequency converting means mayinclude a bandpass filtering means for extracting the positive andnegative frequency components of fs/2 included in the complex basebandsignal.

In the above timing extractor, the frequency converting means mayinclude a numerical operation means for calculating upon every twosamplings a true value multiplied by {square root}{square root over (2)}as the positive and negative frequency components of fs/2 converted tothe frequency position fm.

In the above timing extractor, the nonlinear processing means mayinclude two multiplying means for squaring the I signal and the Q signalresulting from frequency conversion by the frequency converting means,respectively, an adder for adding the I and Q signals squared by themultiplying means, a bit shifting means for multiplying an output of theadder by ½, and a selecting means for selecting the output of the adderor an output of the bit shifting means.

In the above timing extractor, the frequency extracting means may outputthe timing signal once every L times when the frequency position fm is|fm|=fs/(2²×L) (where L is an integer of at least one).

In the above timing extractor, the first and second frequency shiftingmeans each may include a filtering means for removing in advance aninterference component which is present in the frequency position fm.

In the above timing extractor, the frequency converting means maycomplex add respective outputs of the first and second frequencyshifting means.

According to the present invention, a method for extracting a timingcomponent for determining a symbol from a digital modulated signalhaving a symbol rate fs includes the step of converting positive andnegative frequency components of fs/2 included in a complex basebandsignal to a frequency position fm (0<|fm|<fs/2). The complex basebandsignal is obtained from the digital modulated signal and formed from anI signal and a Q signal. The method further includes the steps of: atleast squaring the I signal and the Q signal resulting from thefrequency conversion; adding the squared I and Q signals; and extractingfrom the added signal a frequency component 2fm, i.e., a frequencycomponent which is twice the frequency position fm, as a timing signal.

In the above method, the frequency position fm may be |fm|=fs/2M (whereM is an integer of at least two).

A demodulator according to the present invention includes: an antennafor receiving a digital modulated signal; a semi-synchronous wavedetecting means for quadrature-detecting the digital modulated signalreceived by the antenna to obtain a complex baseband signal formed froman I signal and a Q signal; an A-to-D converting means for convertingthe complex baseband signal obtained by the semi-synchronous wavedetecting means from analog to digital values; and the timing extractor.The digital complex baseband signal obtained by the A-to-D convertingmeans is sampled at a sampling frequency 2fs based on a timing signalfrom the timing extractor, whereby demodulated data is obtained.

According to the present invention, the positive and negative frequencycomponents of fs/2 included in the complex baseband signal are convertedto the frequency position fm. The frequency position fm is smaller thanhalf the symbol rate fs. In other words, 2fm is smaller than fs.Therefore, even though the sampling frequency is 2fs, the positive andnegative frequency components of fs/2 converted to the frequencyposition fm will not interfere with aliasing distortion componentsaccording to the sampling theorem, and power consumption can be reduced.Moreover, since the frequency component fs is extracted by squaring,i.e., by nonlinear processing, timing extraction can be stably conductedwithout being affected by a carrier frequency offset.

In particular, according to the present invention, complexmultiplication to be implemented by frequency conversion of thefrequency operation means can be implemented by the bit shifting meansand the selecting means of the nonlinear processing means. This enablesreduction in circuit scale.

Moreover, according to the present invention, the timing extractor needonly output a timing signal once every L times. This enables significantreduction in operation amount per unit time in a timing error detectorand a loop filter which are provided in a subsequent stage.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram showing the structure of a demodulator using atiming extraction method according to a first embodiment of the presentinvention;

FIG. 2 is a block diagram showing a specific example of the structure ofa timing extracting section according to the first embodiment;

FIG. 3 shows frequency characteristics illustrating operation principlesof a frequency converting section according to the first embodiment,wherein (a) shows a spectrum of a complex baseband signal after rateconversion, (b) shows frequency components ±fs/2 converted to frequencypositions ±fs/4, and (c) shows frequency components ±fs/4 converted todirect current components and frequency components ±fs/2;

FIG. 4 is a block diagram showing a specific example of the structure ofthe frequency converting section according to the first embodiment;

FIG. 5 shows frequency characteristics illustrating operation of thefrequency converting section according to the first embodiment, wherein(a) shows a frequency component −fs/2 of a complex baseband signalconverted to a frequency position −fs/4, (b) shows a frequency component+fs/2 converted to a frequency position −fs/4, (c) shows frequencycharacteristics of a first complex filter, and (d) shows frequencycharacteristics of a second complex filter;

FIG. 6 is a block diagram showing a specific example of the structure ofa ±fs/4 shifting section according to the first embodiment;

FIG. 7 is a block diagram showing a specific example of the structure ofa complex filter according to the first embodiment;

FIG. 8 is waveform diagrams showing the relation between a timing signaland sample points, where (a) shows a waveform obtained when the samplingtiming is late and (b) shows a waveform obtained when the samplingtiming is early;

FIG. 9 is a block diagram showing a specific example of the structure ofa frequency converting section according to a second embodiment;

FIG. 10 shows frequency characteristics illustrating operation of thefrequency converting section according to the second embodiment, where(a) shows a frequency component −fs/2 of a complex baseband signalconverted to the zero frequency position, (b) shows a frequencycomponent +fs/2 converted to the zero frequency position, (c) showsfrequency characteristics of a LPF, and (d) shows other frequencycharacteristics of the LPF;

FIG. 11 is a block diagram showing a specific example of the structureof a frequency converting section according to a third embodiment;

FIG. 12 is a block diagram showing a specific example of the structureof a timing extracting section according to a fourth embodiment;

FIG. 13 is a block diagram showing a specific example of the structureof a frequency converting section according to the fourth embodiment;

FIG. 14 is a block diagram showing a specific example of the structureof a timing extracting section according to a fifth embodiment;

FIG. 15 is a block diagram showing a specific example of the structureof a frequency converting section according to the fifth embodiment;

FIG. 16 is a waveform diagram showing the relation between a timingoutput signal of the timing extracting section according to the fifthembodiment and sample points;

FIG. 17 shows input/output characteristics showing a specific example ofan error function of a timing error detector; and

FIG. 18 shows the overall structure of a demodulator using avoltage-controlled oscillator according to a sixth embodiment.

BEST MODE FOR CARRYING OUT THE INVENTION

Hereinafter, embodiments of the present invention will be described indetail with reference to the accompanying drawings.

FIRST EMBODIMENT

FIG. 1 is a block diagram showing the structure of a demodulator fordemodulating a digital modulated signal such as a QPSK (Quadrature PSK)signal and a QAM signal by a timing extraction method of the firstembodiment of the present invention.

The demodulator will now be described. In FIG. 1, an antenna 101receives a digital modulated signal. A down converter 102 converts thesignal received by the antenna 101 to a desired intermediate frequencyband and outputs the resultant signal.

A semi-synchronous wave detector (semi-synchronous wave detecting means)103 quadrature-detects the received signal at a fixed oscillationfrequency of a local oscillator 104, and outputs in-phase and quadraturecomponents of the signal. Low pass filters (LPFs) 105, 106 removeharmonic components from a complex baseband signal formed from thein-phase and quadrature components received from the semi-synchronouswave detector 103, and output the resultant signal. A-to-D converters(A-to-D converting means) 107, 108 sample the complex baseband signalreceived from the LPFs 105, 106 by using a clock signal higher thantwice a symbol rate fs, and convert the complex baseband signal fromanalog to digital values.

A rate converter 109 converts the rate of the digital complex basebandsignal from the A-to-D converters 107, 108 based on a timing controlsignal 110 a from a timing control section 110 (the timing controlsection 110 will be described later), and outputs the resultant signalat a sampling rate 2fs.

Digital filters (RX-FILs) 111, 112 receive the signal from the rateconverter 109, shape the spectrum of the received signal so as toprevent intersymbolic interference in digital data transmission, andoutput the resultant signal. A waveform equalizer 113 equalizes a ghostwaveform produced by reflection in a transmission path or the like, andoutputs the resultant signal. A synchronous wave detector 114 corrects acarrier frequency offset and outputs demodulated data.

A timing control section 110 receives from the rate converter 109 thecomplex baseband signal formed from the in-phase signal (I) and thequadrature signal (Q) at the sampling rate 2fs, and outputs a timingcontrol signal 110 a to the rate converter 109. The timing controlsection 110 and the rate converter 109 thus form a feedback loop. Thetiming control section 110 includes a timing extracting section 20, atiming error detector 21, and a loop filter 22.

The timing extracting section (timing extractor) 20 extracts timingcomponents for determining symbols from the complex baseband signalreceived from the rate converter 109, and outputs the extracted timingcomponents to the timing error detector 21.

FIG. 2 shows a specific example of the structure of the timingextracting section 20. The timing extracting section 20 includes afrequency converting section 30, two multipliers (multiplying means) 31,32, an adder (adding means) 33, and a bandpass filter (BPF) 34.

A specific operation example of the frequency converting section(frequency converting means) 30 will now be described briefly withreference to (a) and (b) of FIG. 3. In FIG. 3, (a) shows a spectrum ofthe complex baseband signal after rate conversion. In (a) of FIG. 3,dashed line indicates a spectrum of a digital modulated signal, andsolid line indicates ±fs/2 frequency components which are present in thedigital modulated signal changing at a symbol rate fs.

The frequency converting section 30 receives the complex baseband signalfrom the rate converter 109, and converts ±fs/2 frequency components to±fs/4 as shown in (b) of FIG. 3 in order to prevent interference withfrequency components of other frequency domains.

A nonlinear processing section (nonlinear processing means) 40 includesthe two multipliers 31, 32 and the adder 33. The nonlinear processingsection 40 squares (nonlinearly processes) I signal and Q signal of thecomplex baseband signal. More specifically, the multipliers 31, 32square the I signal and the Q signal, respectively, and the adder 33adds the results. As a result of this nonlinear processing, thefrequency components ±fs/4 are converted to direct current componentsand frequency components ±fs/2 as shown in (c) of FIG. 3. The centerfrequency of pass band of the BPF 34 is ±fs/2 as shown by dashed line in(c) of FIG. 3. The BPF 34 receives the nonlinearly processed signal,extracts the frequency components ±fs/2, and outputs the extractedfrequency components as a timing signal.

The frequency components ±fs/2 thus extracted as a timing signal arelarger than −fs and smaller than +fs at the sampling frequency 2fs.Therefore, the frequency components ±fs/2 can be extracted by thenonlinear processing without being affected by aliasing distortioncomponents of the frequency components ±fs/2 themselves.

FIG. 4 shows a specific example of the structure of the frequencyconverting section 30. The frequency converting section 30 includes a+fs/4 shifting section 301, −fs/4 shifting section 302, first and secondcomplex filters (filtering means) 303, 304, and a complex adder 305.

Operation of the frequency converting section 30 will now be describedwith reference to FIG. 5. The complex baseband signal is applied to the+fs/4 shifting section 301 and the −fs/4 shifting section 302. The +fs/4shifting section 301 shifts the frequency of the complex baseband signalby +fs/4. In other words, the +fs/4 shifting section 301 converts thefrequency component −fs/2 of the complex baseband signal in (a) of FIG.3 to a frequency position −fs/4 as shown in (a) of FIG. 5, and suppliesthe resultant signal to the first complex filter 303.

FIG. 6 shows an example of the internal structure of the +fs/4 shiftingsection 301.

In FIG. 6, the +fs/4 shifting section 301 includes a complex multiplier3011 and a sine/cosine signal generator 3012. The sine/cosine signalgenerator 3012 outputs a rotation vector which rotates by π/4 in acomplex plane of I-axis and Q-axis upon every sampling at the samplingclock frequency 2fs. More specifically, the sine/cosine signal generator3012 sequentially and repeatedly supplies to the complex multiplier 3011the I and Q signals having the following values: (I, Q)=(1, 0),(1/{square root}{square root over (2)}, 1/{square root}{square root over(2)}), (0, 1), (−1/{square root}{square root over (2)}, 1/{squareroot}{square root over (2)}), (−1, 0), (−1/{square root}{square rootover (2)}, −1/{square root}{square root over (2)}), (0, −1), (1/{squareroot}{square root over (2)}, −1/{square root}{square root over (2)}).The complex multiplier 3011 complex multiplies the complex basebandsignal and the output signal of the sine/cosine generator 3012.Frequency shifting by +fs/4 can thus be implemented.

The −fs/4 shifting section 302 shifts the frequency of the complexbaseband signal by −fs/4. In other words, the −fs/4 shifting section 302converts the frequency component +fs/2 of the complex baseband signal toa frequency position +fs/4 as shown in (b) of FIG. 5, and supplies theresultant signal to the second complex filter 304. The −fs/4 shiftingsection 302 has the same structure as shown in FIG. 6. The sine/cosinesignal generator 3012 outputs a rotation vector which rotates by −π/4 ina complex plane of I-axis and Q-axis upon every sampling. Morespecifically, the sine/cosine signal generator 3012 sequentially andrepeatedly supplies to the complex multiplier 3011 the I and Q signalshaving the following values: (I, Q)=(1, 0), (1/{square root}{square rootover (2)}, −1/{square root}{square root over (2)}), (0, −1), (−/{squareroot}{square root over (2)}, −1/{square root}{square root over (2)}),(−1, 0), (−1/{square root}{square root over (2)}, 1/{square root}{squareroot over (2)}), (0, 1), (1/{square root}{square root over (2)},1/{square root}{square root over (2)}). Frequency shifting by −fs/4 canthus be implemented.

The first complex filter 303 of FIG. 4 has the following frequencycharacteristics: the first complex filter 303 passes at least afrequency component −fs/4 therethrough, blocks a frequency component+fs/4 in order to prevent interference with the frequency component+fs/4 which is the output of the second complex filter 304, and alsoblocks frequency components ±3fs/4 which will become aliasing distortioncomponents of frequency components ±fs/2 by nonlinear processing in thesubsequent stage. The first complex filter 303 filters the complexbaseband signal according to these frequency characteristics, andsupplies the resultant signal to the complex adder 305. This filteringoperation is an operation of passing a frequency −fs/2 and blocking zerofrequency and frequency components +fs/2 and ±fs in the complex basebandsignal applied to the frequency converting section 30.

FIG. 7 shows an example of the internal structure of the first complexfilter 303. In FIG. 7, the first complex filter 303 includes threecomplex delaying units 41, 42, 43, four complex operation units 44, 45,46, 47, and a complex adder 48. The complex delaying units 41 to 43delay the complex baseband signal according to the sampling clockfrequency 2fs. The complex operation units 44 to 47 perform to thecomplex baseband signal and complex tap coefficients Cim, Cqm (m=0, 1,2, 3) an operation corresponding to complex multiplication. The complexadder 305 adds the outputs of the complex operation units 44 to 47 andoutputs the sum. The frequency characteristics of FIG. 5(c) can beimplemented by providing the following complex tap coefficients: (Ci0,Cq0)=(1, 0), (Ci1, Cq1)=(1/{square root}{square root over (2)},−1/{square root}{square root over (2)}), (Ci2, Cq2)=(0, −1), and (Ci3,Cq3)=(−1/{square root}{square root over (2)}, −1/{square root}{squareroot over (2)}).

The second complex filter 304 of FIG. 4 has the following frequencycharacteristics: the second complex filter 304 passes at least afrequency component +fs/4 therethrough, blocks a frequency component−fs/4 in order to prevent interference with the frequency component−fs/4 which is the output of the first complex filter 303, and alsoblocks frequency components ±3fs/4 which will become aliasing distortioncomponents of frequency components ±fs/2 by nonlinear processing in thesubsequent stage. The second complex filter 304 filters the complexbaseband signal according to these frequency characteristics, andsupplies the resultant signal to the complex adder 305. This filteringoperation is an operation of passing a frequency component +fs/2 andblocking zero frequency and frequency components −fs/2 and ±fs in thecomplex baseband signal applied to the frequency converting section 30.For example, the second complex filter 304 has the internal structure ofFIG. 7, and the frequency characteristics in (d) of FIG. 5 can beimplemented by providing the following tap coefficients: (Ci0, Cq0)=(1,0), (Ci1, Cq1)=(1/{square root}{square root over (2)}, 1/{squareroot}{square root over (2)}), (Ci2, Cq2)=(0, 1), and (Ci3,Cq3)=(−1/{square root}{square root over (2)}, 1/{square root}{squareroot over (2)}).

The complex adder 305 of FIG. 4 complex adds the complex basebandsignals obtained by the above processing. The complex adder 305 thusoutputs the complex baseband signal having the frequency components±fs/2 of the digital modulated wave converted to the frequency positions±fs/4 in order to prevent interference with frequency components ofother frequency domains.

Referring back to FIG. 2, the multipliers 31, 32 of the nonlinearprocessing section 40 respectively square the I and Q signals of thecomplex baseband signal received from the complex adder 305 of thefrequency converting section 30 of FIG. 4, and outputs the resultant Iand Q signals. The adder 33 adds the resultant I and Q signals andsupplies the sum to the BPF 34.

The operation of obtaining the sum of squares in the nonlinearprocessing section 40 is a conventional nonlinear processing method.More specifically, this operation cancels the influences of the factthat the phases of zero degree and 180 degrees of the frequencycomponents become indeterminate due to change of symbol and theinfluences of a carrier frequency offset. Moreover, the presentembodiment cancels a frequency offset which is generated in the +fs/4shifting section 301 and the −fs/4 shifting section 302 in the frequencyconverting section 30 of FIG. 4 due to the sampling frequency lag andtime lag.

The BPF 34 of FIG. 2 extracts the frequency components ±fs/2 from thesignal received from the adder 33 of the nonlinear processing section40, and outputs the extracted frequency components to the timing errordetector 21 of FIG. 1 as a timing signal.

FIG. 8 shows waveform diagrams showing the relation between a timingwaveform and sample points. Curve A in (a) and (b) of FIG. 8 shows awaveform obtained when the sampling timing is correct, curve B in (a) ofFIG. 8 shows a waveform obtained when the sampling timing is late, andcurve C in (b) of FIG. 8 shows a waveform obtained when the samplingtiming is early. For example, the timing error detector 21 detects thetiming difference of a sample point by obtaining φ=Tan⁻¹(X/Y) from thevalues of the points X and Y. The timing error detector 21 then outputsthe detected timing difference to the loop filter 22 as a timing errorsignal.

FIG. 17 shows an error function of the timing error detector 21. In FIG.17, solid line shows the relation between an input phase of a timingsignal and φ=Tan⁻¹(X/Y). It can be seen from FIG. 17 that there are zerocrossing points at the input phase of zero and +π. Pseudosynchronizationoccurs when the input phase converges to +π or −π. In order to preventsuch pseudosynchronization, the timing error detector 21 includes, e.g.,a counter for counting four samples as a pseudosynchronizationpreventing means. The timing error detector 21 analyzes the timingsignal by using four samples of the sampling clock frequency 2fs as onecycle. The timing error detector 21 thus produces such characteristicsas shown by dashed line or chain dotted line in the figure when theinput phase is in the range of π/2 to π and −π/2 to −π. Note that it isdesirable that the initial phase of the rotation vector (zero to 2π)used in the +fs/4 shifting section 301 and the −fs/4 shifting section302 of the frequency converting section 30 of FIG. 4 is zero and thedata point at the time the rotation vector is zero or π is used as areference point of the four samples.

Another method for preventing pseudosynchronization uses a signalquality detecting means such as a BER measuring unit and a C/N detector.Pseudosynchronization is determined to have occurred if the signalquality is poor after a timing control loop converged. In this case, theoutput signal of the rate converter 109 is controlled so that the timingsignal is shifted by π or −π.

The loop filter 22 in the timing control section 110 of FIG. 1 smoothesthe timing error signal received from the timing error detector 21, andoutputs the resultant signal to the rate converter 109 as a timingcontrol signal 110 a.

As has been described above, the structure of the present embodimentenables stable timing extraction at the sampling clock frequency 2fswithout being affected by a carrier frequency offset.

Note that, in the present embodiment, the frequency converting section30 converts the frequency component +fs/2 of the complex baseband signalto the frequency position +fs/4 and converts the frequency component−fs/2 to the frequency position −fs/4. However, the present invention isnot limited to this. For example, the same effects can be obtained evenwhen the frequency converting section 30 converts the frequencycomponents to the opposite frequency positions in order to preventinterference between frequency components. In other words, the frequencyconverting section 30 may convert the frequency component +fs/2 to thefrequency position −fs/4 and convert the frequency component −fs/2 tothe frequency position +fs/4.

SECOND EMBODIMENT

Hereinafter, the second embodiment of the present invention will bedescribed with reference to FIGS. 9 and 10.

The overall structure of the present embodiment is the same as thatshown in FIGS. 1 and 2 except the structure of the frequency convertingsection 30. FIG. 9 shows the structure of the frequency convertingsection 30 of the present embodiment. Note that, in FIG. 9, the sameportions as those of FIG. 4 are denoted with the same reference numeralsand description thereof will be omitted. The portions different fromthose of FIG. 4 will be mainly described below.

In FIG. 9, a complex baseband signal is applied to a +fs/2 shiftingsection (first frequency shifting means) 306 for shifting the frequencyby +fs/2 in the frequency increasing direction and a −fs/2 shiftingsection (second frequency shifting means) 307 for shifting the frequencyby −fs/2 in the frequency decreasing direction. The +fs/2 shiftingsection 306 shifts the frequency of the complex baseband signal by+fs/2. The +fs/2 shifting section 306 thus converts the frequencycomponent −fs/2 of the complex baseband signal in (a) of FIG. 3 to thezero frequency position as shown in (a) of FIG. 10, and supplies theresultant signal to an LPF 308. On the other hand, the −fs/2 shiftingsection 307 shifts the frequency of the complex baseband signal by−fs/2. The −fs/2 shifting section 307 thus converts the frequencycomponent +fs/2 of the complex baseband signal to the zero frequencyposition as shown in (b) of FIG. 10, and supplies the resultant signalto an LPF 309.

The LPFs 308, 309 are the filters having the following frequencycharacteristics: the LPFs 308, 309 pass zero frequency therethrough andblock the frequency components ±fs/2 and ±fs as shown in (c) of FIG. 10.The LPFs 308, 309 filter the complex baseband signal according to thesefrequency characteristics, and supply the resultant signal to a −fs/4shifting section (second frequency shifting means) 310 and a +fs/4shifting section (first frequency shifting means) 311, respectively.

Since the LPFs 308, 309 have the same frequency characteristics, theseLPFs have the same structure. Since the frequency characteristics of theLPFs are positive-and-negative symmetric with respect to zero frequency,each LPF 308, 309 can conduct the same, independent filtering operationto the I signal and the Q signal.

The filtering operation of the LPF 308 is an operation of passing thefrequency component −fs/2 therethrough and blocking zero frequency andthe frequency components +fs/2 and ±1fs in the complex baseband signalapplied to the frequency converting section 30. The filtering operationof the LPF 309 is an operation of passing the frequency component +fs/2therethrough and blocking zero frequency and the frequency components−fs/2 and ±fs in the complex baseband signal applied to the frequencyconverting section 30.

In FIG. 9, the −fs/4 shifting section 310 shifts a zero frequencycomponent to the frequency position −fs/4, shifts a null frequencycomponent of fs to the frequency position 3fs/4, and shifts a nullfrequency component of fs/2 to the frequency position fs/4. On the otherhand, the +fs/4 shifting section 311 shifts a zero frequency componentto the frequency position fs/4, shifts a null frequency component of −fsto the frequency position −3fs/4, and shifts a null frequency component−fs/2 to the frequency position −fs/4.

The complex adder 305 complex adds the respective outputs of the −fs/4shifting section 310 and the +fs/4 shifting section 311. The complexadder 305 thus outputs the complex baseband signal having the frequencycomponents ±fs/2 of the digital modulated wave converted to thefrequency positions ±fs/4 in order to prevent interference withfrequency components of other frequency domains, and having as nullfrequency components the frequency components ±3fs/4 which will becomealiasing distortion components of the frequency components ±fs/4 by thenonlinear processing in the subsequent stage.

As has been described above, according to the present embodiment, thetwo LPFs 308, 309 have the same structure, and each of the LPFs 308, 309has the same, independent filtering structure on its I side and Q side.This simplifies the circuitry. Other specific effects are the same asthose of the first embodiment.

It should be understood that, like the first embodiment, the sameeffects can be obtained even when the frequency converting section 30converts the frequency components ±fs/2 of the complex baseband signalto the opposite frequency positions ±fs/4 in order to preventinterference between frequency components.

THIRD EMBODIMENT

The third embodiment of the present invention will now be described withreference to FIGS. 10 and 11.

The overall structure of the present embodiment is the same as thatshown in FIGS. 1 and 2 except the structure of the frequency convertingsection 30. FIG. 11 shows the structure of the frequency convertingsection 30 of the present embodiment. Note that, in FIG. 11, the sameportions as those of FIGS. 4 and 9 are denoted with the same referencenumerals, and description thereof will be omitted.

In FIG. 11, a complex baseband signal is applied to a BPF (bandpassfiltering means) 312. The center frequency of pass band of the BPF 312is ±fs/2. The BPF 312 receives the complex baseband signal, extracts thefrequency components ±fs/2, and outputs the extracted frequencycomponents to a +fs/2 shifting section 306 and a −fs/2 shifting section307.

The +fs/2 shifting section 306 shifts the frequency of the complexbaseband signal by +fs/2. The +fs/2 shifting section 306 thus convertsthe frequency component −fs/2 to the zero frequency position, convertsthe frequency component +fs/2 to the frequency position fs, and outputsthe resultant signal to an LPF 313. On the other hand, the −fs/2shifting section 307 shifts the frequency of the complex baseband signalby −fs/2. The −fs/2 shifting section 307 thus converts the frequencycomponent +fs/2 to the zero frequency position, converts the frequencycomponent −fs/2 to the frequency position −fs, and outputs the resultantsignal to an LPF 309.

The LPFs 313, 314 are the filters having such frequency characteristicsthat the LPFs 313, 314 pass zero frequency therethrough and block thefrequency components 35 fs as shown in (d) of FIG. 10. The LPFs 313, 314filter the complex baseband signal according to these frequencycharacteristics, and supply the resultant signal to a −fs/4 shiftingsection 310 and a +fs/4 shifting section 311, respectively.

The −fs/4 shifting section 310 shifts a zero frequency component to thefrequency position −fs/4, and shifts a null frequency component of fs tothe frequency position 3fs/4. On the other hand, the +fs/4 shiftingsection 311 shifts a zero frequency component to the frequency positionfs/4, and shifts a null frequency component of −fs to the frequencyposition −3fs/4.

A complex adder 305 complex adds the respective outputs of the −fs/4shifting section 310 and the fs/4 shifting section 311. The complexadder 305 thus outputs the complex baseband signal having the frequencycomponents ±fs/2 of the digital modulated wave converted to thefrequency positions ±fs/4 in order to prevent interference withfrequency components of other frequency domains, and having as nullfrequency components the frequency components ±3fs/4 which will becomealiasing distortion components of the frequency components ±fs/4 by thenonlinear processing in the subsequent stage.

As has been described above, according to the present embodiment, theBPF 312 extracts the frequency components ±fs/2. Therefore, unnecessaryfrequency signal components can be removed in advance, therebystabilizing timing extraction. Other specific effects are the same asthose of the first embodiment.

It should be understood that replacing the frequency characteristics ofthe two LPFs 313, 314 with the frequency characteristics of the LPFs308, 309 shown in (c) of FIG. 10 enables further removal of aliasingdistortion components of the sampling theorem, thereby furtherstabilizing timing extraction.

It should also be understood that, like the first embodiment, the sameeffects can be obtained even when the frequency converting section 30converts the frequency components ±fs/2 of the complex baseband signalto the opposite frequency positions ±fs/4 in order to preventinterference between frequency components.

FOURTH EMBODIMENT

The fourth embodiment of the present invention will now be describedwith reference to FIGS. 12 and 13.

The overall structure of the present embodiment is the same as that ofFIG. 1 except the structure of the timing extracting section 20 of FIG.2. FIG. 12 shows the structure of the timing extracting section 20 ofthe present embodiment.

The timing extracting section 20 of FIG. 12 has the same input/outputsignals as the first to third embodiments described above, but isdifferent from the first to third embodiments in that the frequencyconverting section 30 is replaced with a frequency converting section35, and that a nonlinear processing section 40′ has a bit shifter (bitshifting means) 36 and a selector (selecting means) 37 inserted afterthe adder 33. Note that, in FIG. 12, the same portions as those of FIG.2 are denoted with the same reference numerals, and description thereofwill be omitted.

FIG. 13 shows the structure of the frequency converting section 35. Thefrequency converting section 35 of FIG. 13 is slightly different instructure from the frequency converting section 30 of FIG. 11. In FIG.13, the same portions as those of FIG. 11 are denoted with the samereference numerals, and the portions different from FIG. 11 will bedescribed below.

In FIG. 13, a first numerical operation unit (numerical operation means)315 receives a complex baseband signal from the LPF 313. The firstnumerical operation unit 315 sequentially and repeatedly complexmultiplies the complex baseband signal by the I and Q signals of thefollowing values in a complex plane of I axis and Q axis: (I, Q)=(1, 0),(1/{square root}{square root over (2)}, −1/{square root}{square rootover (2)}), (0, −1), (−1/{square root}{square root over (2)}, −1/{squareroot}{square root over (2)}), (−1, 0), (−1/{square root}{square rootover (2)}, 1/{square root}{square root over (2)}), (0, 1), (1/{squareroot}{square root over (2)}, 1/{square root}{square root over (2)}), andthen complex multiplies only components having the value 1/{squareroot}{square root over (2)} of the I and Q signals of the resultantsignal by {square root}{square root over (2)}. In other words, the firstnumerical operation unit 315 sequentially and repeatedly complexmultiplies the complex baseband signal by the I and Q signals of thefollowing values in the complex plane: (I, Q)=(1, 0), (1, −1), (0, −1),(−1, −1), (−1, 0), (−1, 1), (0, 1), (1, 1).

On the other hand, a second numerical operation unit (numericaloperation means) 316 complex multiplies a complex baseband signal fromthe LPF 314 by I and Q signals having only components with the value1/{square root}{square root over (2)} multiplied by {square root}{squareroot over (2)}, rather than sequentially and repeatedly complexmultiplying the complex baseband signal by the I and Q signals of thefollowing values in a complex plane of I axis and Q axis: (I, Q)=(1, 0),(1/{square root}{square root over (2)}, 1/{square root}{square root over(2)}), (0, 1), (−1/{square root}{square root over (2)}, 1/{squareroot}{square root over (2)}), (−1, 0), (−1/{square root}{square rootover (2)}, −1/{square root}{square root over (2)}), (0, −1), (1/{squareroot}{square root over (2)}, −1/{square root}{square root over (2)}). Inother words, the second numerical operation unit 316 sequentially andrepeatedly complex multiplies the complex baseband signal by the I and Qsignals of the following values in the complex plane: (I, Q)=(1, 0), (1,1), (0, 1), (−1, 1), (−1, 0), (−1, −1), (0, −1), (1, −1).

A control signal generator 317 of FIG. 13 is used to synchronize theoperation timing of the values multiplied by {square root}{square rootover (2)} between the first numerical operation unit 315 and the secondnumerical operation unit 316. For example, according to the controlsignal generator 317, provided that A(n) is a value to be complexmultiplied for the n^(th) sample in the first numerical operation unit315 and B(n) is a value to be complex multiplied for the n^(th) samplein the second numerical operation unit 316, A(n)=(1, 0), A(n+1)=(1, −1),A(n+2)=(0, −1), A(n+3)=(−1, −1), A(n+4)=(−1, 0), A(n+5)=(−1, 1),A(n+6)=(0, 1), A(n+7)=(1, 1), and B(n)=(1, 0), B(n+1)=(1, 1), B(n+2)=(0,1), B(n+3)=(−1, 1), B(n+4)=(−1, 0), B(n+5)=(−1, −1), B(n+6)=(0, −1),B(n+7)=(1, −1).

This complex multiplication of the values and the complex basebandsignal can be implemented by a selector, sign inversion, an adder andthe like without using complex multiplication.

Squaring a value multiplied by {square root}{square root over (2)}equals two. In other words, an original signal can be obtained bysquaring the signal multiplied by {square root}{square root over (2)} inthe frequency converting section 35 and then multiplying the squaredsignal by ½. As shown in FIG. 12, in the nonlinear processing section40′, the signal is squared, and then multiplied by ½ in the bit shifter36. The output of the bit shifter 36 or the output of the adder 33 isselected based on the timing of the control signal generator 317. Morespecifically, the output signal of the bit shifter 36 is selected at thetiming of the signals multiplied by {square root}{square root over (2)},and the output of the adder 33 is selected at the timing of othersignals. In this way, the same output as the timing extracting section20 of FIG. 2 can be obtained.

As has been described above, according to the present embodiment, asignal squared and then multiplied by ½ or an output signal having anormal value is selected based on the control signal. By using thisstructure, the operation to be performed by a complex multiplier can beimplemented only by the adder 33, the bit shifter 36 and the selector37. This enables reduction in circuit scale.

Other specific effects are the same as those of the first embodiment. Itshould be understood that, like the first embodiment, the same effectscan be obtained even when the frequency converting section 35 convertsthe frequency components ±fs/2 of the complex baseband signal to theopposite frequency positions ±fs/4 in order to prevent interferencebetween frequency components.

FIFTH EMBODIMENT

The fifth embodiment of the present invention will now be described withreference to FIGS. 14 and 15.

The overall structure of the present embodiment is the same as that ofFIG. 1 except the structure of the timing extracting section 20 of FIG.2. FIG. 14 shows the structure of the timing extracting section 20 ofthe present embodiment.

The timing extracting section 20 of FIG. 14 has the same input signalsas the first embodiment of FIG. 2, but is different from the firstembodiment in that the frequency converting section 30 is replaced witha frequency converting section 38, and that the BPF 34 of FIG. 12 isreplaced with a BPF 39 having a center frequency of pass band of ±fs/4.Note that, in FIG. 14, the same portions as those of FIG. 2 are denotedwith the same reference numerals, and description thereof will beomitted.

FIG. 15 shows the structure of the frequency converting section 38. Thefrequency converting section 38 is different from the frequencyconverting section 30 of FIG. 11 in that the −fs/4 shifting section 310is replaced with a −fs/8 shifting section 318 and that the +fs/4shifting section 311 is replaced with a +fs/81 shifting section 319. InFIG. 15, the same portions as those of FIG. 11 are denoted with the samereference numerals, and only the different portions will be describedbelow.

The −fs/8 shifting section 318 of FIG. 15 shifts a frequency componentproduced with a change of a symbol located at the zero frequencyposition to the frequency position −fs/8. On the other hand, the +fs/8shifting section 319 shifts a frequency component produced with a changeof a symbol located at the zero frequency position to the frequencyposition fs/8.

A complex adder 305 complex adds the respective outputs of the −fs/8shifting section 318 and the +fs/8 shifting section 319. The complexadder 305 thus outputs a complex baseband signal having as nullfrequency components the frequency components ±7fs/8 which will becomealiasing distortion components of the frequency components ±fs/4 by thenonlinear processing in the subsequent stage, without causinginterference by the frequency components ±fs/8.

The two multipliers 31, 32 of FIG. 14 respectively square the I and Qsignals of the complex baseband signal received from the complex adder305 of the frequency converting section 38. The adder 33 adds thesquared I and Q signals. This nonlinear processing converts thefrequency components ±fs/8 of the input signal to the zero frequencyposition and the frequency positions ±fs/4. The BPF 39 extracts thefrequency components ±fs/4 and outputs the extracted frequencycomponents as a timing signal.

FIG. 16 is a waveform showing the relation between the timing signal andsample intervals. In the first to fourth embodiments, the timing signalis represented by four sampling points in each cycle of the sine wave,as shown in FIG. 8. In the present embodiment, however, the timingsignal is represented by eight sampling points in each cycle of the sinewave, as shown in FIG. 16. For example, by outputting as a timing signalthe signal with the sample data of black circles in the figure removed(alternate sample data), the timing error detector 22 and the loopfilter 22 in the subsequent stage need only operate based on thisthinned-out timing signal. This enables reduction in operation amountper unit time.

As has been described above, according to the present embodiment, theoutput data of the BPF 39 can be thinned out, thereby enabling reductionin operation amount per unit time of the timing error detector 22 andthe loop filter 23 of the subsequent stage. Other specific effects arethe same as those of the first embodiment.

It should be understood that, like the first embodiment, the sameeffects can be obtained even when the frequency converting section 38converts the frequency components ±fs/2 of the complex baseband signalto the opposite frequency positions ±fs/8 in order to preventinterference between the frequency components.

In the present embodiment, the frequency components ±fs/2 of the complexbaseband signal applied to the timing extracting section 20 areconverted to the frequency positions ±fs/8, and the frequency components±fs/4 are extracted after nonlinear processing. However, the presentinvention is not limited to this. It should be understood that the sameeffects as those of the first embodiment can be obtained even when thefrequency components ±fs/2 are converted to frequency positions ±fs/2M(where M is an integer of three or more) and frequency components ±fs/Mare extracted after nonlinear processing. The integer M may not be used.The frequency components ±fs/2 included in the complex baseband signalneed only be converted to a frequency position fm (0<|fm|<fs/2) so thatthe frequency components ±fs/2 do not interfere with other frequencycomponents.

By converting the frequency components ±fs/2 to frequency positions±fs/(2²×L), extracting frequency components ±fs/(2×L) after nonlinearprocessing (where L is an integer of three or more), and outputting thedata once every L times to the timing error detector 22, the operationamount of the timing error detector 22 and the loop filter 23 in thesubsequent stage can further be reduced.

SIXTH EMBODIMENT

The sixth embodiment of the present invention will now be described withreference to FIG. 18.

FIG. 18 shows another example of the structure of the demodulatorincluding the timing extractor of the present invention. The demodulatorof FIG. 18 includes a D-to-A converter 115 and a voltage-controlledclock oscillator 116 instead of the rate converter 109 of FIG. 1. Unlikethe demodulator of FIG. 1, the demodulator of FIG. 18 conducts timingcontrol by using a feedback loop formed by the A-to-D converters 107,108, the timing control section 110, the D-to-A converter 115 and thevoltage-controlled clock oscillator 116.

The differences between the demodulator of FIG. 18 and the demodulatorof FIG. 1 will now be described briefly. The A-to-D converters 107, 108sample a complex baseband signal in response to a clock supplied fromthe voltage-controlled clock oscillator 116. This clock is twice thesymbol rate fs. The A-to-D converters 107, 108 thus convert the complexbaseband signal from analog to digital values.

The timing control section 110 receives the complex baseband signal. Thetiming extracting section 20 then extracts timing, and the timing errordetector 21 detects a sample timing error generated in the A-to-Dconverters 107, 108. The loop filter 22 smoothes the timing error andoutputs the resultant signal as a timing control signal. The D-to-Aconverter 115 converts the timing control signal received from the loopfilter 22 to an analog signal. The voltage-controlled clock oscillator116 is capable of controlling a clock oscillation frequency by a voltagevalue. The voltage-controlled clock oscillator 116 receives the timingcontrol signal from the D-to-A converter 115 as a voltage value, andsupplies to the A-to-D converters 107, 108 a clock having a frequency atwhich the timing control signal is stable.

As a result, operation can be conducted at a desired sample timing,whereby stable demodulation can be implemented.

INDUSTRIAL APPLICABILITY

As has been described above, according to the timing extractor and thetiming extracting method of the present invention, the timing componentsfor determining symbols are extracted from a digital modulated signal byusing a sampling frequency which is twice the symbol rate fs. Even withsuch a sampling frequency, the timing components can be stably extractedwithout causing any interference with aliasing distortion components andwithout being affected by a carrier frequency offset. The presentinvention is therefore useful for applications such as modulation ofdigital modulation systems used in digital satellite TV broadcasting,digital cable TV broadcasting and the like.

1. A timing extractor for extracting a timing component for determininga symbol from a digital modulated signal having a symbol rate fs,comprising: a frequency converting means for converting positive andnegative frequency components of fs/2 included in a complex basebandsignal to a frequency position fm (0<|fm|<fs/2), the complex basebandsignal being obtained from the digital modulated signal and formed froman I signal and a Q signal; a nonlinear processing means for at leastsquaring the I signal and the Q signal resulting from frequencyconversion by the frequency converting means; and a frequency extractingmeans for extracting from an output signal of the nonlinear processingmeans a frequency component 2fm, i.e., a frequency component which istwice the frequency position fm, and outputting the extracted frequencycomponent as a timing signal.
 2. The timing extractor according to claim1, wherein the frequency position fm is |fm|=fs/2M (where M is aninteger of at least two).
 3. The timing extractor according to claim 2,wherein M=2 and the frequency position fm is |fm|=fs/4.
 4. The timingextractor according to claim 2, wherein M=4 and the frequency positionfm is |fm|=fs/8.
 5. The timing extractor according to claim 1 or 2,wherein the frequency converting means includes a filtering means forremoving in advance from the complex baseband signal a frequencycomponent which will become an aliasing distortion component for thefrequency component 2fm included in the output signal of the nonlinearprocessing means.
 6. The timing extractor according to claim 1, whereinthe frequency converting means includes a first frequency shifting meansfor shifting a frequency of the complex baseband signal in a frequencyincreasing direction, and a second frequency shifting means for shiftinga frequency of the complex baseband signal in a frequency decreasingdirection.
 7. The timing extractor according to claim 1, 2 or 6, whereinthe frequency converting means includes a frequency shifting means forshifting a frequency of the complex baseband signal in a frequencyincreasing direction and a frequency decreasing direction by fs/2. 8.The timing extractor according to claim 1, wherein the frequencyconverting means includes a bandpass filtering means for extracting thepositive and negative frequency components of fs/2 included in thecomplex baseband signal.
 9. The timing extractor according to claim 3,wherein the frequency converting means includes a numerical operationmeans for calculating upon every two samplings a true value multipliedby {square root}{square root over (2)} as the positive and negativefrequency components of fs/2 converted to the frequency position fm. 10.The timing extractor according to claim 9, wherein the nonlinearprocessing means includes two multiplying means for squaring the Isignal and the Q signal resulting from frequency conversion by thefrequency converting means, respectively, an adder for adding the I andQ signals squared by the multiplying means, a bit shifting means formultiplying an output of the adder by ½, and a selecting means forselecting the output of the adder or an output of the bit shiftingmeans.
 11. The timing extractor according to claim 1 or 2, wherein thefrequency extracting means outputs the timing signal once every L timeswhen the frequency position fm is |fm|=fs/(2²×L) (where L is an integerof at least one).
 12. The timing extractor according to claim 6, whereinthe first and second frequency shifting means each includes a filteringmeans for removing in advance an interference component which is presentin the frequency position fm.
 13. The timing extractor according toclaim 6, wherein the frequency converting means complex adds respectiveoutputs of the first and second frequency shifting means.
 14. A methodfor extracting a timing component for determining a symbol from adigital modulated signal having a symbol rate fs, comprising the stepsof: converting positive and negative frequency components of fs/2included in a complex baseband signal to a frequency position fm(0<|fm|<fs/2), the complex baseband signal being obtained from thedigital modulated signal and formed from an I signal and a Q signal; atleast squaring the I signal and the Q signal resulting from thefrequency conversion; adding the squared I and Q signals; and extractingfrom the added signal a frequency component 2fm, i.e., a frequencycomponent which is twice the frequency position fm, as a timing signal.15. The method according to claim 14, wherein the frequency position fmis |fm|=fs/2M (where M is an integer of at least two).
 16. Ademodulator, comprising: an antenna for receiving a digital modulatedsignal; a semi-synchronous wave detecting means for quadrature-detectingthe digital modulated signal received by the antenna to obtain a complexbaseband signal formed from an I signal and a Q signal; an A-to-Dconverting means for converting the complex baseband signal obtained bythe semi-synchronous wave detecting means from analog to digital values;and the timing extractor according to claim 1, wherein the digitalcomplex baseband signal obtained by the A-to-D converting means issampled at a sampling frequency 2fs based on a timing signal from thetiming extractor, whereby demodulated data is obtained.